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| TP5208 64K SRAM ECHO PROCESSOR General Description The TP5208 is a developed processor for producing echo effects added to voice signals picked up by microphone for karaoke applications. The IC has the largest memory among the digital delay series. As its design is aimed at high performance, it is best suited to provide radio cassette tape recorders and miniature unit audio system with quality echo function. With pins compatible with the Mitsubishi Features Built-in input/output filters, A-D and D-A converters and memory realize a delay system with only a single chip Capable of composing low-noise and low-distortion delay system at low cost by ADM system (No = -88dB typ, THD = 0.17% typ) Control mode selections available from 2 kinds: easy mode using parallel data and microcomputer mode using serial data Sleep mode can be selected to stop IC functions Built-in automatic reset circuit M65831AP/FP, M65830CP/FP, and M65843AP/FP, the TP5208 is suitable for upgrading the series. Pin Configuration VDD XIN XOUT D1/REQ D2/SCK D3/DATA D4/IDSW TEST EASY/U-COM SLEEP D-GND A-GND 1 2 3 4 5 6 7 8 9 10 11 12 24 PINS DIP/SOP 24 23 22 21 20 19 18 17 16 15 14 13 VCC LPF1 IN LPF1 OUT OP1 OUT OP1 IN REF CC1 CC2 OP2 IN OP2 OUT LPF2 IN LPF2 OUT Data Sheet - Version 1.1 January 2005 Page 1 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VDD XIN XOUT D1/REQ D2/SCK D3/DATA D4/IDSW TEST EASY/U-COM SLEEP DGND AGND LPF2 OUT LPF2 IN OP2 OUT OP2 IN CC2 CC1 REF OP1 IN OP1 OUT LPF1 OUT LPF1 IN VCC Pin Name Digital VDD Oscillator input Oscillator input Delay1/Request Delay2/Shift clock Delay3/Serial data Delay4/ID switch Test EASY/U-COM Sleep Digital GND Analog GND Low pass filter2 output Low pass filter2 input OP-AMP2 output OP-AMP2 input Current control 2 Current control 1 Reference OP-AMP1 input OP-AMP1 output Low pass filter1 output Low pass filter1 input Analog VCC I/O I O I I I I I I I O I O I I O O I Description Supply voltage Connects to 2MHz ceramic filter Easy mode: inputs D1 data U-COM mode: inputs request data Easy mode: inputs D2 data U-COM mode: inputs shift clock Easy mode: inputs D3 data U-COM mode: inputs shift data Easy mode: inputs D4 data U-COM mode: controls ID code L = normal mode H = Easy mode; L = U-COM mode H = sleep mode; L = normal mode Connects to analog GND at one point Connects to analog GND Forms low pass filter with external C, R Forms integrator with external C, R = 1/2 VCC Forms integrator with external C, R Forms low pass filter with external C, R Supply voltage Functional Description EASY Mode (EASY/U-COM = H) D4 L L L L L L L L H H H H H H H H D3 L L L L H H H H L L L L H H H H D2 L L H H L L H H L L H H L L H H D1 L H L H L H L H L H L H L H L H fs 666 666 666 666 666 666 666 666 333 333 333 333 333 333 333 333 Td 12.3 24.6 36.9 49.2 61.4 73.7 86.0 98.3 110.6 122.9 135.2 147.5 159.7 172.0 184.3 196.6 NOTES: f s: Sampling Frequency (KHz) Td: Delay Time (msec) Data Sheet - Version 1.1 January 2005 Page 2 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR U-COM Mode (EASY/U-COM = L) H Delay Time H = MUTE ID Code = SLEEP Mode This timing chart shows that delay time is set by serial data from U-COM. DATA signal is latched at the falling edge of SCK signal; the last ten data are set at the rising edge of REQ signal when ID codes are satisfied. ID1, ID3: L ID2: H ID4: equal to IDSW REQ, SCK, DATA Input Timing Symbol t1 ds t2 t3 t4 t5 Parameter SCK Pulse Width SCK Pulse Duty DATA Setup Time DATA Hold Time REQ Hold Time REQ Pulse Width Min 250 100 100 100 250 Limit Typ 50 t1/2 t1/2 Max Unit ns % ns ns ns ns MUTING EASY mode Automatic mute upon changing delay time, canceling SLEEP mode and power-on. U-COM mode MUTE = H: mute MUTE = L: automatic mute Data Sheet - Version 1.1 January 2005 Page 3 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Automatic Mute 1. Upon Changing Delay Time Delay Signal Before Change Mode Delay Signal After Change Mode 2. Upon Canceling SLEEP Mode Delay Signal 3. Upon Power-On Delay Signal Power On SLEEP Mode SLEEP data is H: clock and RAM stop to reduce circuit current (SLEEP mode) L: normal operation System Reset Automatically reset power-on. The reset time is about 120msec and the delay time is set at 147.5msec. Data Sheet - Version 1.1 January 2005 Page 4 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Absolute Maximum Ratings (Ta = 25J Parameter Supply Voltage Supply Current Power Dissipation Operating Temperature Storage Temperature Symbol Vcc Icc Pd Topr Tstg , unless otherwise noted) Ratings 6.5 100 1.7 -20 ~ +75 -25 ~ +125 Unit V mA W J J Recommended Operating Conditions Parameter Supply Voltage Supply Voltage Difference Voltage Clock Frequency High Input Voltage Low Input Voltage Symbol VCC VDD VCC - VDD fck VIH VIL Limit Min 4.5 4.5 -0.3 1 0.7VDD Typ 5 5 0 2 Max 5.5 5.5 0.3 3 0.3VDD Unit V V V MHz V V AC Electrical Characteristics (VCC = 5.0V, fin = 1KHz, Vi = 100mVrms, fck = 2MHz, Ta = 25J Parameter Circuit Current Voltage gain Maximum Output Voltage Output Distortion Mute Time Output Noise Voltage Symbol Icc Gv Vomax THD TMUTE No Limit Min 1.0 508 508 Typ 36 -0.5 1.6 0.17 0.4 528 528 -88 Max 50 2.5 0.8 1.2 548 548 -80 Unit mA dB Vrms % % ms ms dBV , unless otherwise noted) Test Condition No Signal RL = 47K THD = 10% fs = 666KHz 30KHz L.P.F. fs = 333Khz Upon Changing Delay Time Upon Canceling Sleep Mode DIN-AUDIO (fs = 333KHz) DC Electrical Characteristics Parameter Supply Voltage Supply Current High Input Voltage Low Input Voltage Symbol Vcc Icc VIH VIL Limit Min 4.5 0.7VDD Typ 5 60 Max 5.5 80 0.3VDD Unit V mA V V Data Sheet - Version 1.1 January 2005 Page 5 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Application EASY Mode IN 1u 10k 10k 1u 20k 30k 0.01u 3k 22nF 10k 0.047u 0.01u 0.047u 47u 0.33u 22nF 620 2.2nF 0.33u 620 10k 2.2nF 1u 2.7k OUT 24 Vcc 23 LPF1_in 22 LPF1_out 21 OP1_out 20 OP1_in 19 REF 18 CC1 17 CC2 16 EASY/u_com OP2_in 15 OP2_out 14 LPF2_in 13 LPF2_out 22nF SLEEP DGND 1 2M Hz 100u 0.1u 2 3 4 5 6 7 8 TEST 9 10 11 100p 100p SETING DELAY TIME U-COM Mode 20k IN 1u 10k 10k 1u 30k 0.047u 47u 0.01u 3k 0.01u 10k 0.047u 620 10k 2.2nF 1u 2.7k AGND XOUT VDD XIN D4 D1 D2 D3 12 22nF 620 0.33u 0.33u OUT 2.2nF 24 Vcc 23 LPF1_in 22 LPF1_out 21 OP1_out 20 OP1_in 19 REF 18 CC1 17 CC2 16 EASY/u_com OP2_in 15 OP2_out 14 LPF2_in 13 LPF2_out AGND SLEEP XOUT DATA IDSW 1 2M Hz 100u 0.1u 2 3 4 5 6 7 8 TEST VDD REQ SCK XIN 9 10 11 DGND 12 100p 100p u-COM Data Sheet - Version 1.1 January 2005 Page 6 of 7 http://www.topro.com.tw TP5208 64K SRAM ECHO PROCESSOR Package Information TP5208P (24-pin DIP) * Headquarters 5 F, No. 10, Prosperity Road 1, Science-Based Industrial Park, Hsinchu, Taiwan 300, R.O.C. Tel.: +886-3-563-2515 Fax: +886-3-564-1728 * Taipei Office 2 F, No. 26, Lane 583, Ruiguang Rd., Neihu, Taipei, Taiwan 114, R.O.C. Tel.: +886-2-2627-6222 Fax: +886-2-2657-0256 * Shenzhen Office Room 802, Tower A, World Trade Plaza, No. 9, Fuhong Rd., Futian, Shenzhen, China Tel.: +86-755-8367-9985 Fax: +86-755-8367-9518 Data Sheet - Version 1.1 January 2005 Page 7 of 7 http://www.topro.com.tw |
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